It has been approved by both theory and empirical studies that when a stress is applied to the channel of a transistor, strain is produced in the semiconductor lattice in a channel region, then the carrier mobility of the transistor will be enhanced or reduced; however, it is also known that electrons and holes may have different responses to the same type of strain. For example, application of compressive stress in a longitudinal direction of flow of electrical current causes compressive strain to occur in the lattice in the channel region, which is advantageous for enhancing the hole mobility, but the electron mobility is correspondingly decreased. Application of tensile stress in the longitudinal direction causes tensile strain to occur in the lattice in the channel region, which is advantageous for enhancing the electron mobility, but the hole mobility is correspondingly decreased. With continuous reduction in the device feature size, strain channel engineering for the purpose of enhancing the channel carrier mobility plays a more and more important role. Multiple uniaxial process induced strains are integrated to a device process. In terms of the optimal introducing direction of the uniaxial process induced strain, as for an NMOS device, introduction of tensile strain in a direction along the channel, that is, direction X as well as introduction of compressive strain in a direction perpendicular to the channel, that is, direction Z are most effective for enhancing the mobility of electrons in the channel, as shown in FIG. 1; on the other hand, as for a PMOS device, introduction of compressive strain in the direction X is most effective for enhancing the mobility of holes in the channel. A lot of methods have been developed based on this theory. One of the methods is to produce “global strain”, that is, the stress, which is produced from the substrate, is applied to the overall transistor device area. The global strain is produced by using the following structures such as a global strain silicon layer formed by epitaxially growing materials of SiGe and SiC etc. of different lattice constants on a buffer layer which is on an ordinary substrate and further growing thereon a low-defect single crystal silicon layer, or the SiGe structure and strained silicon structure on an insulator realized by using the method of manufacturing the silicon on an insulator. Another method is to produce “local strain”, that is, using the local structure that is adjacent to the device channel or the technique thereof to produce a corresponding stress to be applied to the channel region to produce strain, local strain is generally produced by using the following structures such as shallow trench isolation structure that produces a stress, (dual) stress liner, SiGe structure embedded into source/drain (S/D) region of a PMOS (e-SiGe), Σ-shaped SiGe structure embedded into source/drain (S/D) region of a PMOS, and SiC structure embedded into the source/drain (S/D) region of an NMOS (e-SiC). However, among the above methods for producing channel local strain and changing the type of strain act on the channel, some require a complicated process, and some may introduce defects to the channel. On the other hand, with continuous reduction in the device feature size, the induced strain effect brought forward by the above method is continuously weakened.
In view of the above reasons, there still exists a need for introducing a new method and semiconductor structure for realizing enhanced strain for both tiny sized NMOS device and PMOS device, furthermore control of the level and type of introduced strain is also needed.